1. Technological Field
The described technology relates to the field of memory arrangements. More specifically it relates to memory arrangements with memory elements having a nano-electro-mechanical switch as memory element.
2. Description of the Related Technology
Memory arrangements are widely researched and a large number of specific configurations are known. A category of interest for a large set of applications are non-volatile memory arrangements.
Recently, attention has been drawn to nano-electro-mechanical (NEM) switches, which are promising devices providing opportunities for use both in logic circuits and as memories, either standalone or combined with other technologies such as CMOS. One example of a non-volatile memory bit cell and an array thereof is described in U.S. Patent Publication No. 2009/0273962. The non-volatile memory bit cell described therein is a four terminal cell having a pull-up electrode, a pull-down electrode, a cantilever electrode and a contact electrode. Furthermore a NMOS transistor can be coupled to the contact electrode.
It is however not trivial to create a compact, reliable NEMS memory array that is sufficiently fast and that consumes a low energy per access, both for read and write.
There is a demand for high density, high access speed, and low energy consuming memory arrays, having these properties both for read and write operations.